(1) Field of the Invention
The present invention relates to the manufacture of ultra large scale integrated (ULSI) circuit chips in general, and in particular, to a high selectivity etching stop layer for damascene process.
(2) Description of the Related Art
Damascene process, which is an adaptation of an old Middle Eastern art form where a work piece was scratched with a sharp tool to form a desired pattern and then filled with gold or silver and the excess metal rubbed off with a piece of rag, is used to great advantage especially in the manufacturing of ultra scale integrated (ULSI) semiconductor devices. Whereas in ancient work, the damascene process was used essentially to form a single layer of a desired pattern--hence a single damascene process--the application of the same process to fabricating a metal layer and the connecting layer together has brought forth the real advantages of what is now called dual damascene process.
It is well known in the art of manufacturing semiconductor substrates that one of the major challenges is the building of multi-levels of metal and insulating layers with accurate registration of one layer with respect to the other. This requires that the layers are extremely flat and well planarized so that the subsequent layers can be optically aligned to the previous layers. As the feature sizes are being scaled down dramatically with the advance of ultra scale registration, it is becoming more and more difficult to fill in between sub-micron features, such as between metal lines, with insulating materials. Even if they can be filled, the insulating materials formed over features replicate the features themselves to the extent that the resulting surface is not planar. Planarization can be performed in any number of ways, such as reflowing the material, or abrading to a flat surface by polishing, or by chemical mechanical polishing, all of which, still make the resulting surface not flat to the required levels, or that contaminants, and other defects are imparted to the surface from the planarizing equipment and processes. With a damascene process, the starting point is with a flat surface into which trenches and holes are formed by etching, and no further planarization is necessarily required.
Thus, the damascene process itself is a technique where metal interconnections are inlaid in preformed grooves in a substrate, and is usually a preferred method of fabricating interconnections for integrated circuits. In contrast, the more conventional interconnections are formed by blanket depositing a conductive material on an insulation layer such as silicon oxide, and then etching the desired wiring pattern on the layer. The vertical connections between the wiring layers are made separately by forming holes in the insulation layers separating the metallized layers and then filling them with the same or a different conductive material.
Normally, a semiconductor substrate contains passive and active regions having active devices formed near the surface of the semiconductor substrate. The active devices are interconnected through an interlevel conductive layer. One or more metal wiring layers are then formed overlying the interlevel dielectric layer and are separated from each other by additional insulating layers. The wiring stripes are connected to each other and to the devices at the appropriate places by means of holes that are filled with metal through the insulating layers. The holes that connect the metal lines to each other through the insulating layer are called via holes, while the holes that reach the underlying devices through its insulating layer are called contact holes. Typically, the holes are etched into an insulating layer after the latter has been deposited on the semiconductor substrate on which the chips are fabricated. It is common practice to next blanket deposit metal on the insulating layer thereby filling the holes and then forming the metal lines by etching through a patterned photo resist mask formed on the metal layer. For the first metal layer, electrical contact is made with the underlying devices through contact holes, or windows, that allow the metal to descend through the dielectric insulator to the devices. For the second and subsequent wiring layers, the process is repeated and the contact between the metal layers is made through via holes that allow the metal to descend to the lower metal layer(s). It is also common practice to fill the holes separately with metal to form metal plugs first, planarize or smoothen them next with respect to the surface of the insulating layer and then deposit metal layer to make contact with the via plugs and then subtractively etch as before to form the required "personalized" wiring layer.
The more advanced process of forming interconnects with dual damascene is illustrated in FIGS. 1a-1d where, in addition to forming the grooves of single damascene, conductive via openings are also formed. In FIG. 1a of prior art, two layers of insulating layer, that is, lower layer (30) and upper layer, (40), are shown deposited on a first level interconnect metal layer (25) already formed on substrate (10). There is usually an etch stop layer between layers (30) and (40), depicted as reference to numeral (43).
In this conventional dual damascene process, then, insulating layer (30) is coated with a photoresist (not shown) which is exposed through a first mask with image pattern of the via openings (35) and the pattern is anisotropically etched in upper insulating layer (40), that is, down to the etch stop layer. The photoresist now is exposed through a second mask with an image pattern of the conductive line openings, after being aligned with the first mask pattern to encompass the via openings. In anisotropically etching the opening for the conductive ones in the upper insulating layer, the via openings (35) already present in the upper insulating layer are simultaneously etched and replicated in the lower layer of insulating materiel (30). After the etching is complete, both the vias, (35), and line openings, or trenches, (45), are filled with metal (50) as shown in FIG. 1c. Finally, excess metal (50) is removed to arrive at the structure shown in FIG. 1d.
Dual damascene is an improvement over single damascene because it permits the filling of both the trenches and the vias with metal at the same time, thereby eliminating process steps. Although this conventional dual damascene offers advantages over other processes for forming interconnections, it has a number of shortcomings, such as forming and filling the via holes. For example, the edges of via openings in the lower insulating layer, after the second etching, are poorly defined because of the two etchings. It will be apparent to those skilled in the art that etching plays a significant role in a damascene process. The integrity and dimensional control of holes and trenches are governed to a large extent by the etching process that is used, as well as on the materials that are being etched.
Etch stop layer (43) in FIG. 1a is an etch barrier film such as silicon nitride (SiN) to prevent the upper line trench patterns of dual damascene from being etched through subsequent etch steps if the layer underlying the composite insulation layer is for via plug hole or contact isolation. Other barrier films may be used, however silicon nitride is generally preferred because it becomes part of the composite insulation layer and has different etch characteristics than that of silicon dioxide (SiO.sub.2) or phosphosilicate glass (PSG) layers that can be used as insulation layers. That is, silicon nitride allows a selective etch process with respect to different underlying materials. Spin-on-glass and CVD nitride are also suitable as etch-stop materials when polyimide layers are used.
Silicon nitride is generally deposited by either high temperature (700-800.degree. C.) low-pressure (LPCVD) technique, or low temperature plasma enhanced (PECVD). However, PECVD silicon nitride tends to be nonstoichiometric, while LPCVD nitride exhibits high tensile stresses, causing cracks for films greater that about 2000 .ANG.. Silicon nitride also exhibits outgassing which result in voids and, therefore, reliability problems. Furthermore, etch rates for silicon nitride are relatively fast so that for relatively low selectivity of silicon nitride to oxides in general, nitride layers must be thick. This results in cracks.
Some of these problems have been addressed in prior art as they relate to semiconductor manufacturing, in general. For example, Armacost, et al., in U.S. Pat. No. 5,662,596 uses a stoichiometrically altered Si.sub.3 N.sub.4 as an etch stop layer. This etch stop layer is characterized by a nitride formed stoichiometrically with the addition of some materials, such as silicon and hydrogen, which impart improved etch selectivity over SiO.sub.2. For damascene processes, in particular, etch stops of specific characteristics need to be developed. Because there are at least two etchings that are required to define both line trenches and interconnect holes in a damascene process, the integrity of the interface where one etch stops and the other starts must be preserved in order to have robust damascene structures with undegraded electrical resistances at the interfaces. In U.S. Pat. No. 5,635,423, Huang, et al., teach a modified dual damascene process where an opening for a via is initially formed in a second insulating layer above a first insulating layer with an etch stop layer therebetween. A larger opening for a trench is then formed in the second insulating layer while simultaneously extending the via opening through the etch stop layer and first insulating layer. He uses commonly used materials such as silicon nitride as the etch stop layer but without any alterations to suit the needs of the dual damascene process. Similarly, Mu, et al., disclose a method of forming an interconnect on a semiconductor substrate, and specifically on a silicon nitride layer. However, none of the prior art address the thickness of the etch stop layer and the concomitant cracking problem.
The present invention discloses a high selectivity etching stop layer with a specific chemistry and smaller thickness so as to prevent cracking during damascene process.